{"title":"设计和使用基于阵列的测试结构来表征由WLCSP焊料凸起引起的机械应力效应","authors":"H. Tuinhout, R. van Dalen","doi":"10.1109/ICMTS.2016.7476175","DOIUrl":null,"url":null,"abstract":"This paper discusses a 2100-DUT-array based test structure approach for high-resolution characterization of spatial mechanical stress distributions that are attributable to wafer level chip scale package solder bumps. DUT cell layout requirements, array implementation, measurement approach, and some data analysis challenges are reviewed in detail. Several examples of solder bump induced mobility variation illustrate the value of these test structures.","PeriodicalId":344487,"journal":{"name":"2016 International Conference on Microelectronic Test Structures (ICMTS)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Design and use of an array-based test structure to characterize mechanical stress effects caused by WLCSP solder bumps\",\"authors\":\"H. Tuinhout, R. van Dalen\",\"doi\":\"10.1109/ICMTS.2016.7476175\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper discusses a 2100-DUT-array based test structure approach for high-resolution characterization of spatial mechanical stress distributions that are attributable to wafer level chip scale package solder bumps. DUT cell layout requirements, array implementation, measurement approach, and some data analysis challenges are reviewed in detail. Several examples of solder bump induced mobility variation illustrate the value of these test structures.\",\"PeriodicalId\":344487,\"journal\":{\"name\":\"2016 International Conference on Microelectronic Test Structures (ICMTS)\",\"volume\":\"3 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2016-03-28\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2016 International Conference on Microelectronic Test Structures (ICMTS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICMTS.2016.7476175\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 International Conference on Microelectronic Test Structures (ICMTS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICMTS.2016.7476175","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Design and use of an array-based test structure to characterize mechanical stress effects caused by WLCSP solder bumps
This paper discusses a 2100-DUT-array based test structure approach for high-resolution characterization of spatial mechanical stress distributions that are attributable to wafer level chip scale package solder bumps. DUT cell layout requirements, array implementation, measurement approach, and some data analysis challenges are reviewed in detail. Several examples of solder bump induced mobility variation illustrate the value of these test structures.
求助内容：
应助结果提醒方式：
京公网安备 11010802042870号
