在后摩尔定律世界中抓住封装互连的带宽扩展

Grigory Chirkov, D. Wentzlaff
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引用次数: 2

摘要

摩尔定律的缓慢和预测的终结迫使设计师们不再仅仅考虑增加晶体管,而是鼓励他们利用其他未使用的资源来提高芯片性能。同时,近年来,芯片间互连技术取得了巨大的飞跃,极大地增加了可用带宽。虽然摩尔定律的终结将不可避免地减缓单芯片设置的性能进步,但互连技术可能会继续扩展。我们设想未来设计人员必须创造方法来利用互连来获得更好的系统性能。作为一个将互连利用率转化为性能的特性的例子,我们提出了Meduza -一个用于未来芯片系统的写更新一致性协议。Meduza将以前的写更新协议扩展到具有多级缓存层次结构的系统。与基于芯片的系统上的MESIF一致性协议相比,Meduza在我们的基准套件中的执行速度提高了19%。此外,Meduza承诺在未来的系统中会有更多的优势。这项工作表明,通过利用多余的互连带宽,在现代和未来的芯片系统中有额外性能的巨大潜力。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Seizing the Bandwidth Scaling of On-Package Interconnect in a Post-Moore's Law World
The slowing and forecasted end of Moore's Law have forced designers to look beyond simply adding transistors, encouraging them to employ other unused resources as a manner to increase chip performance. At the same time, in recent years, inter-die interconnect technologies made a huge leap forward, dramatically increasing the available bandwidth. While the end of Moore's Law will inevitably slow down the performance advances of single-die setups, interconnect technologies will likely continue to scale. We envision a future where designers must create ways to exploit interconnect utilization for better system performance. As an example of a feature that converts interconnect utilization into performance, we present Meduza - a write-update coherence protocol for future chiplet systems. Meduza extends previous write-update protocols to systems with multi-level cache hierarchies. Meduza improves execution speed in our benchmark suite by 19% when compared to the MESIF coherence protocol on a chiplet-based system. Moreover, Meduza promises even more advantages in future systems. This work shows that by exploiting excess interconnect bandwidth, there is significant potential for additional performance in modern and future chiplet systems.
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