存在线电感的互连建模

M. El-Moursy, H. Shawkey
{"title":"存在线电感的互连建模","authors":"M. El-Moursy, H. Shawkey","doi":"10.1142/S021812661250082X","DOIUrl":null,"url":null,"abstract":"Simple uniform reduced order model is used to model an RLC interconnect line. Waveform characterization is used to evaluate the accuracy of the adopted models. As compared to RC lines, less than five times the number of sections is sufficient to model RLC lines. Look-up tables are provided to simplify the process of choosing the best interconnect section model to characterize an RLC interconnect line. The tables are shown to be accurate for wide range of relative impedance of the driver, the line, and the load. The tables provide a simple and quick mean to characterize an RLC interconnect which is necessary for performance evaluation in digital circuits. The presented model reduces the simulation time while keeping the simulation accuracy. The simulation time can be reduced by up to 72% with less than 10% reduction in accuracy using the provided tables.","PeriodicalId":125634,"journal":{"name":"2011 Saudi International Electronics, Communications and Photonics Conference (SIECPC)","volume":"102 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2011-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"Interconnect modeling with the existence of line inductance\",\"authors\":\"M. El-Moursy, H. Shawkey\",\"doi\":\"10.1142/S021812661250082X\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Simple uniform reduced order model is used to model an RLC interconnect line. Waveform characterization is used to evaluate the accuracy of the adopted models. As compared to RC lines, less than five times the number of sections is sufficient to model RLC lines. Look-up tables are provided to simplify the process of choosing the best interconnect section model to characterize an RLC interconnect line. The tables are shown to be accurate for wide range of relative impedance of the driver, the line, and the load. The tables provide a simple and quick mean to characterize an RLC interconnect which is necessary for performance evaluation in digital circuits. The presented model reduces the simulation time while keeping the simulation accuracy. The simulation time can be reduced by up to 72% with less than 10% reduction in accuracy using the provided tables.\",\"PeriodicalId\":125634,\"journal\":{\"name\":\"2011 Saudi International Electronics, Communications and Photonics Conference (SIECPC)\",\"volume\":\"102 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2011-04-24\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2011 Saudi International Electronics, Communications and Photonics Conference (SIECPC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1142/S021812661250082X\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 Saudi International Electronics, Communications and Photonics Conference (SIECPC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1142/S021812661250082X","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3

摘要

采用简单均匀降阶模型对RLC互连线进行建模。波形特性用于评估所采用模型的准确性。与RC线相比,不到五倍的截面数量就足以模拟RLC线。提供了查找表,以简化选择最佳互连截面模型来表征RLC互连线的过程。对于驱动器、线路和负载的相对阻抗的宽范围,表显示是准确的。这些表提供了一种简单快捷的方法来表征RLC互连,这是数字电路性能评估所必需的。该模型在保证仿真精度的同时减少了仿真时间。使用所提供的表,模拟时间最多可减少72%,精度降低不到10%。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Interconnect modeling with the existence of line inductance
Simple uniform reduced order model is used to model an RLC interconnect line. Waveform characterization is used to evaluate the accuracy of the adopted models. As compared to RC lines, less than five times the number of sections is sufficient to model RLC lines. Look-up tables are provided to simplify the process of choosing the best interconnect section model to characterize an RLC interconnect line. The tables are shown to be accurate for wide range of relative impedance of the driver, the line, and the load. The tables provide a simple and quick mean to characterize an RLC interconnect which is necessary for performance evaluation in digital circuits. The presented model reduces the simulation time while keeping the simulation accuracy. The simulation time can be reduced by up to 72% with less than 10% reduction in accuracy using the provided tables.
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