共门级非线性对CMOS级联低噪声放大器线性度的影响

Chenglin Cui, Tae-Sung Kim, Seong-Kyun Kim, Jun-Kyung Cho, Su-Tae Kim, Byung-sung Kim
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引用次数: 11

摘要

本文研究了共门级非线性对级联放大器线性度的影响。传统上,CG级被认为是CMOS级联低噪声放大器(LNA)设计中理想的电流缓冲器,但分析表明,由于CG级的输出电阻有限和级间节点的寄生电容,随着增益的增加,CG级限制了级联LNA的线性度。因此,CS级的简单线性化很难随着工作频率的增加而提高LNA的增益。为了验证这一分析,设计了一个2 GHz的CMOS LNA,并测量了增益和非线性。测量结果表明,正如分析所期望的那样,存在使LNA达到最大OIP3的最佳负载阻抗。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Effects of the nonlinearity of the common-gate stage on the linearity of CMOS cascode low noise amplifier
This work presents the effects of the common-gate (CG) stage nonlinearity on the linearity of the cascode amplifier. Conventionally, the CG stage is assumed as an ideal current buffer in the CMOS cascode low noise amplifier (LNA) design, but the analysis shows that the CG stage limits the linearity of the cascode LNA as the gain increases, due to the finite output resistance of the CG stage and the parasitic capacitance at the interstage node. Therefore, the simple linearization of the CS stage has difficulties to enhance the gain of LNA as the operating frequency increases. To confirm the analysis, a 2 GHz CMOS LNA was designed and the gain and the nonlinearity were measured. The measurement results show that there exists optimum load impedance to achieve the maximum OIP3 of the LNA as expected by the analysis.
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