Embedded zero wavelet coefficient coding method for FPGA implementation of video codec in real-time systems

The issues of video coding based on exceptionally suitable for SHD format Shapiro (1993) EZW (embedded zero wavelet) algorithm is discussed. The main aspect is a possibility of building a real time system which is able to process the algorithm. Thus a dedicated architecture for the purpose is considered. The method presented is based on the EZW method modified such a way to simplify the hardware architecture dedicated for its execution. Such a simplification allows one to use FPGA technology as a target platform for the system. The MISD (multiple instruction-stream single data-stream) architecture is proposed as a solution of the problem. The architecture is characterised by high speed execution of the EZW algorithm. Simplicity and performance classify the algorithm for implementation in high capacity programmable FPGA structures. The paper is the authors contribution in the world's development of custom computing machines (CCM).