有效实现亚20nm节点弱单元感知DRAM容错

Hao Wang, Kai Zhao, Tong Zhang
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摘要

DRAM产业面临的一个巨大挑战是如何继续缩小存储节点宽高比(a /R)以保持存储节点的存储电容。一个可行的选择是故意降低A/R的扩展速度,但代价是不可修复的弱单元不能保证在最坏情况下的目标数据保留时间,并在系统级别补偿弱单元引起的内存错误。尽管可以利用弱单元位置信息的可用性来最大限度地提高弱单元诱导的容错能力,但直接实现弱单元感知的容错能力往往会遭受巨大的内存访问延迟开销,特别是在存在大量弱单元的情况下。本文提出了一种在很小的存储器访问延迟开销下实现弱单元感知容错的设计方案。关键是使用混合错误检测/纠正过程来消除对弱小区位置信息的不必要访问。我们进行了大量的模拟和评估,以证明该设计解决方案的有效性和权衡。除了对延迟开销进行理论分析之外,我们还进一步进行了基于周期精确的x86模拟器和DRAM仿真的全系统仿真,并使用带有板上DRAM芯片的FPGA开发板实现了我们的设计解决方案。结果成功地表明,我们的设计方案可以在非常小(甚至可以忽略不计)的延迟开销下轻松处理高达10-4 ~ 10-3的弱细胞诱导内存错误率。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Efficiently Realizing Weak Cell Aware DRAM Error Tolerance for Sub-20nm Technology Nodes
DRAM industry faces a grand challenge on continuing the scaling of storage node aspect ratio (A/R) to maintain the storage node storage capacitance. One viable option is to intentionally slow down the A/R scaling at the penalty of irreparable weak cells that cannot guarantee target data retention time under worst-case scenarios, and compensate the weak-cell-induced memory errors at the system level. Although the availability of weak cell location information can be leveraged to maximize the weak-cell-induced error tolerance, a straightforward realization of weak cell aware error tolerance tends to suffer from significant memory access latency overhead, especially in the presence of a large number of weak cells. This paper presents a design solution that can realize weak cell aware error tolerance at very small memory access latency overhead. The key is to use a hybrid error detection/correction process to eliminate unnecessary access to the weak cell location information. We carried out extensive simulations and evaluations to demonstrate the effectiveness of this design solution and the trade-offs. Beyond theoretical analysis on the latency overhead, we further performed full-system simulations based upon a cycle-accurate x86 simulator and DRAM simulation, and implemented our design solution using an FPGA development board with on-board DRAM chips. The results successfully show that our design solution can readily handle the weak-cell-induced memory error rate of upto 10-4 ~ 10-3 at very small (even negligible) latency overhead.
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