{"title":"基于三维忆阻器的跨栅结构胶囊网络实现","authors":"Yi Huang, Rui Hu, Z. Zeng","doi":"10.1109/ICIST.2018.8426119","DOIUrl":null,"url":null,"abstract":"Although the Capsule Network (CapsNet) has a better proven performance for the recognition of overlapping digits than Convolutional Neural Networks (CNNs), a large number of matrix-vector multiplications between lower-level and higher-level capsules impede efficient implementation of the CapsNet on conventional hardware platforms. Since three-dimensional (3-D) memristor crossbars provide a compact and parallel hardware implementation of neural networks, this paper provides an architecture design to accelerate convolutional and matrix operations of the CapsNet. By using 3-D memristor crossbars, the PrimaryCaps, DigitCaps, and convolutional layers of a CapsNet perform the matrix-vector multiplications in a highly parallel way. Simulations are conducted to recognize digits from the USPS database and to analyse the work efficiency of the proposed circuits. The proposed design provides a new approach to implement the CapsNet on memristor-based circuits.","PeriodicalId":331555,"journal":{"name":"2018 Eighth International Conference on Information Science and Technology (ICIST)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"Three-Dimensional Memristor-Based Crossbar Architecture for Capsule Network Implementation\",\"authors\":\"Yi Huang, Rui Hu, Z. Zeng\",\"doi\":\"10.1109/ICIST.2018.8426119\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Although the Capsule Network (CapsNet) has a better proven performance for the recognition of overlapping digits than Convolutional Neural Networks (CNNs), a large number of matrix-vector multiplications between lower-level and higher-level capsules impede efficient implementation of the CapsNet on conventional hardware platforms. Since three-dimensional (3-D) memristor crossbars provide a compact and parallel hardware implementation of neural networks, this paper provides an architecture design to accelerate convolutional and matrix operations of the CapsNet. By using 3-D memristor crossbars, the PrimaryCaps, DigitCaps, and convolutional layers of a CapsNet perform the matrix-vector multiplications in a highly parallel way. Simulations are conducted to recognize digits from the USPS database and to analyse the work efficiency of the proposed circuits. The proposed design provides a new approach to implement the CapsNet on memristor-based circuits.\",\"PeriodicalId\":331555,\"journal\":{\"name\":\"2018 Eighth International Conference on Information Science and Technology (ICIST)\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2018-06-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2018 Eighth International Conference on Information Science and Technology (ICIST)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICIST.2018.8426119\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 Eighth International Conference on Information Science and Technology (ICIST)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICIST.2018.8426119","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Three-Dimensional Memristor-Based Crossbar Architecture for Capsule Network Implementation
Although the Capsule Network (CapsNet) has a better proven performance for the recognition of overlapping digits than Convolutional Neural Networks (CNNs), a large number of matrix-vector multiplications between lower-level and higher-level capsules impede efficient implementation of the CapsNet on conventional hardware platforms. Since three-dimensional (3-D) memristor crossbars provide a compact and parallel hardware implementation of neural networks, this paper provides an architecture design to accelerate convolutional and matrix operations of the CapsNet. By using 3-D memristor crossbars, the PrimaryCaps, DigitCaps, and convolutional layers of a CapsNet perform the matrix-vector multiplications in a highly parallel way. Simulations are conducted to recognize digits from the USPS database and to analyse the work efficiency of the proposed circuits. The proposed design provides a new approach to implement the CapsNet on memristor-based circuits.