{"title":"高速串行链路:设计趋势与挑战","authors":"V. Stojanović","doi":"10.1109/IWSOC.2005.72","DOIUrl":null,"url":null,"abstract":"Summary form only given. In this talk we describe design trends in high-speed serial links from two complementary viewpoints. On one hand we have improvements of the channel through microwave engineering of the passive interconnects/backplanes, and on the other hand a trend toward increased sophistication of the serial link circuits, employing more and more of the communications techniques to compensate for the channel and noise. We describe recent breakthroughs in passive backplane design as well as give some predictions about the capacity of the typical backplane interconnect channels. By looking at the target interconnect applications, like 10-100Tb/s routers, it is clear that both the data rate and power have to improve by an order of magnitude each, to achieve the design goal with manageable physical dimensions of the system. This means an improvement of two orders in magnitude in energy cost per bit, from current designs. We believe that the emerging link design trends like multi-tone signaling and channel-and-circuit-aware coding have the promise to fulfil this task.","PeriodicalId":328550,"journal":{"name":"Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2005-07-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"High-speed serial links: design trends and challenges\",\"authors\":\"V. Stojanović\",\"doi\":\"10.1109/IWSOC.2005.72\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Summary form only given. In this talk we describe design trends in high-speed serial links from two complementary viewpoints. On one hand we have improvements of the channel through microwave engineering of the passive interconnects/backplanes, and on the other hand a trend toward increased sophistication of the serial link circuits, employing more and more of the communications techniques to compensate for the channel and noise. We describe recent breakthroughs in passive backplane design as well as give some predictions about the capacity of the typical backplane interconnect channels. By looking at the target interconnect applications, like 10-100Tb/s routers, it is clear that both the data rate and power have to improve by an order of magnitude each, to achieve the design goal with manageable physical dimensions of the system. This means an improvement of two orders in magnitude in energy cost per bit, from current designs. We believe that the emerging link design trends like multi-tone signaling and channel-and-circuit-aware coding have the promise to fulfil this task.\",\"PeriodicalId\":328550,\"journal\":{\"name\":\"Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05)\",\"volume\":\"40 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2005-07-20\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IWSOC.2005.72\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IWSOC.2005.72","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
High-speed serial links: design trends and challenges
Summary form only given. In this talk we describe design trends in high-speed serial links from two complementary viewpoints. On one hand we have improvements of the channel through microwave engineering of the passive interconnects/backplanes, and on the other hand a trend toward increased sophistication of the serial link circuits, employing more and more of the communications techniques to compensate for the channel and noise. We describe recent breakthroughs in passive backplane design as well as give some predictions about the capacity of the typical backplane interconnect channels. By looking at the target interconnect applications, like 10-100Tb/s routers, it is clear that both the data rate and power have to improve by an order of magnitude each, to achieve the design goal with manageable physical dimensions of the system. This means an improvement of two orders in magnitude in energy cost per bit, from current designs. We believe that the emerging link design trends like multi-tone signaling and channel-and-circuit-aware coding have the promise to fulfil this task.