硅功率器件堆叠芯片寄生电阻的测量

2023 35th International Conference on Microelectronic Test Structure (ICMTS) Pub Date : 2023-03-27 DOI:10.1109/ICMTS55420.2023.10094137

T. Ohguro, Hideharu Kojima, T. Hara, T. Nishiwaki, Kenya Kobayashi

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引用次数: 0

摘要

叠芯片的!硅功率器件具有导通电阻低、封装尺寸小等优点，可减小系统尺寸，提高功率效率。本文介绍了叠片寄生电阻的测量方法和结构。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Measuring of parasitic resistance of stacked chip of Si power device

Stacked chip of! Si power device is useful for both lower on-resistance and small packaged size for reduction of system size and high power efficiency. In this paper, some structures and procedure to measure parasitic resistance of the stacked chip are described.

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2023 35th International Conference on Microelectronic Test Structure (ICMTS)

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