可测试CMOS组合逻辑电路的设计

[1988] The Eighteenth International Symposium on Fault-Tolerant Computing. Digest of Papers Pub Date : 1988-06-27 DOI:10.1109/FTCS.1988.5323

S. Kundu, S. Reddy

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引用次数: 90

摘要

作者提出了一种集成的方法来设计组合逻辑电路，其中卡断故障和路径延迟故障可以通过鲁棒测试来检测，该测试可以检测与被测电路中的延迟无关的建模故障。他们证明了所提出的设计和测试保证了CMOS逻辑电路设计中所有路径延迟故障都是可定位的

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On the design of robust testable CMOS combinational logic circuits

The authors propose an integrated approach to the design of combinational logic circuits in which stuck-open faults and path delay faults are detectable by robust tests that detect modeled faults independent of the delays in the circuit under test. They demonstrate that the proposed designs and tests guarantee the design of CMOS logic circuits in which all path delay faults are locatable.<>

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来源期刊

[1988] The Eighteenth International Symposium on Fault-Tolerant Computing. Digest of Papers

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