采用65纳米CMOS技术的浮动接地屏蔽变压器的v波段推推式倍频器

2016 IEEE International Conference on Microwave and Millimeter Wave Technology (ICMMT) Pub Date : 2016-06-05 DOI:10.1109/ICMMT.2016.7761825

Jia. Zhou, J. Wen, G. Su, Xianghong Gao, Meng Jin

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引用次数: 1

摘要

本文提出了一种低功耗v波段倍频器。浮地屏蔽变压器平衡器采用中心电容补偿技术，实现了良好的平衡性能和输入匹配。该倍频器的转换增益(CG)带宽为14 GHz，范围为58至72 GHz，峰值CG为-6.5 dB，峰值效率为7.7%，在64 GHz时输出功率为0 dBm。该倍频器采用65 nm CMOS工艺制造，芯片尺寸为663×492 μm2，功耗为9.6 ~ 12.8 mW。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A V-band push-push frequency doubler using floating-Ground shield transformer in 65-nm CMOS technology

This paper presents a low-power, V-band doubler. A floating-Ground shielding transformer balun achieved a good balanced performance and input matching by using a central capacitor-based compensation technique. The doubler exhibits a 3-dB conversion gain (CG) bandwidth of 14 GHz range from 58 to 72 GHz and demonstrates a peak CG of -6.5 dB and peak efficiency of 7.7% with an output power of 0 dBm at 64 GHz. The doubler is fabricated in 65 nm CMOS process with chip size of 663×492 μm2 and consumes 9.6-12.8 mW power.

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2016 IEEE International Conference on Microwave and Millimeter Wave Technology (ICMMT)

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