Implementation of total dose constraints at the design level of full custom bipolar integrated circuits

This paper presents a design approach in order to deal with total-dose induced degradation with commercial IC processes. Devices behavior limitations are presented, and layout-based techniques are proposed to reduce bipolar transistors radiation sensitivity. The global design procedure combines these layout hardened devices with rad-dedicated design techniques. In addition, a gated lateral PNP has been designed to evaluate the ionizing radiation effects on its electrical characteristics. Its voltage controlled current gain remains sufficiently large once irradiated to expect an effective hardening of the analog function. To illustrate this approach, a commercial BiCMOS integrated circuit has been fabricated in an Austria Mikro Systeme process. The test vehicle revealed a good radiation hardness level.