Engineering the cascoded NMOS output buffer for maximum V/sub t1/

The overall ESD performance of CMOS integrated circuits is often limited by the ESD robustness of the lateral NPN (LNPN) bipolar transistor parasitic to the NMOS output buffer. In this paper, we investigate layout and bias options for maximizing the lateral NPN bipolar trigger voltage V/sub t1/ of the cascoded NMOSFET output buffer. Based on experimental data and device simulations, we demonstrate: (1) how bipolar turn-on characteristics change with buffer layout; and (2) how V/sub t1/ may be significantly increased by applying bias to the upper NMOSFET gate. Example circuits which produce these preferential ESD bias conditions are shown.