Design of HDL Based Low Power Audio Subword Sorter Unit

The security of audio data in high end communication applications like satellites and radars is an issue of concern these days. Designing a processor at the chip level for this requirement is by itself a challenge to VLSI engineers. This paper aims to design a HDL based novel audio subword sorter unit, which is less complex in structure and highly efficient in terms of security. In this paper, we examine the hardware implementation of low power powerful permutation instruction group (GRP). This is done at the integrated chip (IC-level) using Verilog HDL and can be implemented in FPGA. To our knowledge this is the first audio subword sorter unit implemented in FPGA