低功耗高精度可调谐赢家通吃网络

Proceedings of Fifth International Conference on Microelectronics for Neural Networks Pub Date : 1996-02-12 DOI:10.1109/MNNFS.1996.493805

R. Canegallo, M. Chinosi, A. Kramer

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引用次数: 0

摘要

本文介绍了一种低功耗CMOS电路，用于在可调的选择范围内选择n个模拟电压中的最大值。选取范围的幅值采用精度递增-递减规律确定。在2v到4v的动态输入范围内，通过将速度从2mhz降低到500khz，可以获得16mv到4mv的分辨率。静态电流为1 /spl mu/A，所选单元的交流电流为2 /spl mu/A，体积小，可用于大规模并行模拟计算电路的VLSI实现。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A low-power high-precision tunable WINNER-TAKE-ALL network

This paper describes a low power CMOS circuit for selecting the greatest of n analog voltages within a tunable selection range. An increasing speed-decreasing precision law is used to determine the amplitude of the selection range. 16 mV to 4 mV resolution, over a 2 V to 4 V dynamic input range, can be obtained by reducing the speed from 2 MHz to 500 kHz. 1 /spl mu/A quiescent current, 2 /spl mu/A AC current for the selected cells and small size make this circuit available for VLSI implementations of massively parallel analog computational circuits.

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Proceedings of Fifth International Conference on Microelectronics for Neural Networks

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