内存数据重组提高HEVC DCT的性能

2014 International Conference on Electronics, Information and Communications (ICEIC) Pub Date : 2014-10-02 DOI:10.1109/ELINFOCOM.2014.6914388

Hyunwoo Kim, S. Jo, Farhan Hussain, Y. Song

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引用次数: 0

摘要

DCT由于存在大量的重复操作，是HEVC的主要性能瓶颈。通过并行执行这些重复操作，可以提高DCT的性能。但是，访问所需数据的内存操作限制了并行化的性能改进。在本文中，我们利用我们之前的工作开发的ASIP并行化DCT，并提出了一种有效的内存数据重组方案，以进一步提高DCT并行化的性能。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Memory data reorganization for performance improvement of HEVC DCT

DCT is the main performance bottleneck of the HEVC because it has a lot of repeated operations. Performance of the DCT can be improved by executing these repeated operations in parallel. However, memory operations to access the required data limit performance improvements of the parallelization. In this paper, we parallelize the DCT by using the ASIP developed in our previous work and propose an efficient memory data reorganization scheme to achieve further performance improvements of DCT parallelization.

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2014 International Conference on Electronics, Information and Communications (ICEIC)

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