加速算术运算的嵌入式内存处理器体系结构

Richard Muri, P. Fortier
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引用次数: 3

摘要

内存中的处理器(PIM)计算机体系结构是在与内存相同的位置执行某些逻辑操作子集的任何设计。传统的计算模型包括处理器从内存中加载数据来执行操作,处理器和内存之间通过总线连接。虽然这种技术在许多情况下都能很好地工作,但内存性能和处理器性能之间的差距越来越大,这促使一些研究人员开发替代架构。本文详细介绍了PIM架构在软核微控制器中的实现,用于加速受寄存器文件大小限制的应用程序。使用Artix-7 FPGA,将ATmega103微控制器软核修改为包括PIM核作为加速器。AES加密的示例应用程序提供了基线处理器和PIM增强机器之间的比较。使用改进后的微控制器的AES加密需要减少38%的时钟周期,而不依赖于特定应用程序的改进,以增加程序内存大小和FPGA结构利用率为代价。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Embedded Processor-In-Memory Architecture for Accelerating Arithmetic Operations
A processor-in-memory (PIM) computer architecture is any design that performs some subset of logical operations in the same location as memory. The traditional model of computing involves a processor loading data from memory to perform operations, with a bus connecting the processor and memory. While this technique works well in many situations, a growing gap between memory performance and processor performance has led some researchers to develop alternative architectures.This paper details the implementation of a PIM architecture in a soft core microcontroller used to accelerate applications limited by register file size. Using an Artix-7 FPGA, an ATmega103 microcontroller soft core is modified to include a PIM core as an accelerator. The sample application of AES encryption provides a comparison between the baseline processor and the PIM enhanced machine. AES encryption using the modified microcontroller requires 38% fewer clock cycles without relying on application specific improvements, at the expense of increased program memory size and FPGA fabric utilization.
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