Utilizing Frequency Changing in Communication Systems to Reduce Power in CRC Circuits

Modern communication circuits use adaptive modulation techniques to fulfill its task. These techniques require changing the clock frequency of the of the communication units inside the communication circuit. The clock frequency can affect the power consumption of the digital circuits. In this paper, Dynamic Voltage / Frequency Scheduling (DVFS) is modified to use the clock frequency variation so that the CRC stage power is decreased. The DVFS is represented by a fuzzy controller that uses the frequency and the calculated power of the system as its input to calculate the required CRC unite supply voltage. The simulations show that for a 16bit CRC circuit a reduction in power in low frequencies can reach 75 % and the reduction is 4% in high frequencies.