Designing low power high throughput MAC for 802.11AD WLAN SoC

The latest IEEE WLAN 802.11ad standard guarantees the multi giga bit throughput which is highest in the Wireless LAN (WLAN) technology. The system designed for such high performance will pose enough design challenges to make them consume low power. This can however be achieved by adopting low power management and control block in the digital part of the System on Chip (SoC) like Medium Access Control (MAC) which in addition to the standard specified power management MAC sublayer management entity (MLME) feature, implements special control circuitry called Power Management Entity (PME) in the SoC under consideration, which manages power consumption of the logic considering the functionality and the configurations/modes. Apart from this, standard Low power options like power aware hardware partitioning, clock gating, power gating and switching selectively the blocks to low frequency etc. are supported in PME as applied to the WLAN MAC and other SoC blocks in data and control paths. This paper deals with different techniques used in the low power high throughput MAC design along with PME to achieve low power consumption guaranteeing the targeted performance as per the standard and beyond. The resulting architecture promises to give 24 to 26% less power consumption in Access Point (AP) and Station (STA) configurations.