一个新的4-2加法器和展位选择器,用于低功耗MAC单元

Bum-Sik Kim, Daewoong Chung, L. Kim
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引用次数: 4

摘要

随着技术的进步,超大规模集成电路系统的集成度也在不断提高。在数字信号处理系统中,数据处理单元的功耗必须尽可能低。因此,我们采用传输门电路设计了一个4-2加法器和一个展位选择器,在不牺牲性能的情况下实现了低功耗。所提出的4-2加法器比传统4-2加法器功耗低16%,所提出的展位选择器比传统展位选择器功耗低60%。我们设计了一个32位的MAC单元,提出了4-2加法器和摊位选择器。32位MAC单元在100mhz时功耗为124mw,电源为2v,面积为1.3 mm/spl × /2.4 mm。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A new 4-2 adder and booth selector for low power MAC unit
The integration level of VLSI system increases as the technology improves. The power dissipation of the data processing unit in the digital signal processing systems must be kept as low as possible. Thus, we newly designed a 4-2 adder and a booth selector by using transmission gate circuits to accomplish low power consumption without performance sacrifice. The proposed 4-2 adder consumes lower power than the conventional 4-2 adder by 16% and the proposed booth selector consumes less power than the conventional booth selector by 60%. We designed a 32-bit MAC unit with the proposed 4-2 adder and the booth selector. The power dissipation of the 32-bit MAC unit is 124 mW at 100 MHz with 2 V power supply, with the area of 1.3 mm/spl times/2.4 mm.
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