{"title":"快速锁定和高精度电流匹配锁相环","authors":"Silin Liu, Yin Shi","doi":"10.1109/APCCAS.2008.4746225","DOIUrl":null,"url":null,"abstract":"In this paper, a charge-pump based phase-locked loop (CPLL) that can achieve fast locking and tiny deviation is proposed and analyzed. A lock-aid circuit is added to achieve fast locking of the CPLL. Besides, a novel differential charge pump which has good current matching characteristics and a PFD with delay cell has been used in this PLL. The proposed PLL circuit is designed based on the 0.35 um 2P4M CMOS process with 3.3 V/5 V supply voltage. HSPICE simulation shows that the lock time of the proposed CPLL can be reduced by over 72% in comparison to the conventional PLL and its charge pump sink and source current mismatch is only 0.008%.","PeriodicalId":344917,"journal":{"name":"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":"{\"title\":\"Fast locking and high accurate current matching phase-locked loop\",\"authors\":\"Silin Liu, Yin Shi\",\"doi\":\"10.1109/APCCAS.2008.4746225\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, a charge-pump based phase-locked loop (CPLL) that can achieve fast locking and tiny deviation is proposed and analyzed. A lock-aid circuit is added to achieve fast locking of the CPLL. Besides, a novel differential charge pump which has good current matching characteristics and a PFD with delay cell has been used in this PLL. The proposed PLL circuit is designed based on the 0.35 um 2P4M CMOS process with 3.3 V/5 V supply voltage. HSPICE simulation shows that the lock time of the proposed CPLL can be reduced by over 72% in comparison to the conventional PLL and its charge pump sink and source current mismatch is only 0.008%.\",\"PeriodicalId\":344917,\"journal\":{\"name\":\"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2008-11-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"8\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/APCCAS.2008.4746225\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/APCCAS.2008.4746225","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 8
摘要
本文提出并分析了一种基于电荷泵的锁相环(CPLL),该锁相环可以实现快速锁相和微小的误差。通过加锁辅助电路实现CPLL的快速锁定。此外,该锁相环还采用了具有良好电流匹配特性的差分电荷泵和带延迟单元的PFD。本文设计的锁相环电路基于0.35 um 2P4M CMOS工艺,电源电压为3.3 V/5 V。HSPICE仿真结果表明,该CPLL锁相时间比传统锁相环缩短72%以上,电荷泵吸源电流失配率仅为0.008%。
Fast locking and high accurate current matching phase-locked loop
In this paper, a charge-pump based phase-locked loop (CPLL) that can achieve fast locking and tiny deviation is proposed and analyzed. A lock-aid circuit is added to achieve fast locking of the CPLL. Besides, a novel differential charge pump which has good current matching characteristics and a PFD with delay cell has been used in this PLL. The proposed PLL circuit is designed based on the 0.35 um 2P4M CMOS process with 3.3 V/5 V supply voltage. HSPICE simulation shows that the lock time of the proposed CPLL can be reduced by over 72% in comparison to the conventional PLL and its charge pump sink and source current mismatch is only 0.008%.