Thockchom Birjit Singha, Shruti Konwar, Soumik Roy, Reginald H. Vanlalchaka
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The main aim of VLSI designers being low power design, this paper presents a CMOS-based new design approach for a low power adiabatic 4:2 Priority Encoder and a 2:4 Decoder. The proposed designs are compared with the standard adiabatic logic styles- PFAL, ECRL and 2n2n2p, revealing lesser power consumption. The simulation is carried out in NI-Multisim software at 0.5 μm CMOS technology for frequency range 200MHz - 800MHz.
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