{"title":"一种用于移动电子设备节能状态高效循环的快速锁定锁相环结构","authors":"N. August, M. Rifani","doi":"10.1109/ICCE.2009.5012163","DOIUrl":null,"url":null,"abstract":"Extended battery operation and quick wake-up time are important features in mobile consumer electronic devices. When a PLL generates the system clock, acquisition time can consume a significant portion of a sleep cycle, wasting energy that could provide useful processing. This paper presents a PLL architecture that improves lock time by at least an order of magnitude compared to an existing PLL.","PeriodicalId":154986,"journal":{"name":"2009 Digest of Technical Papers International Conference on Consumer Electronics","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A fast-locking PLL architecture for efficient cycling of power-saving states in mobile electronic devices\",\"authors\":\"N. August, M. Rifani\",\"doi\":\"10.1109/ICCE.2009.5012163\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Extended battery operation and quick wake-up time are important features in mobile consumer electronic devices. When a PLL generates the system clock, acquisition time can consume a significant portion of a sleep cycle, wasting energy that could provide useful processing. This paper presents a PLL architecture that improves lock time by at least an order of magnitude compared to an existing PLL.\",\"PeriodicalId\":154986,\"journal\":{\"name\":\"2009 Digest of Technical Papers International Conference on Consumer Electronics\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2009-05-29\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2009 Digest of Technical Papers International Conference on Consumer Electronics\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICCE.2009.5012163\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 Digest of Technical Papers International Conference on Consumer Electronics","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICCE.2009.5012163","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A fast-locking PLL architecture for efficient cycling of power-saving states in mobile electronic devices
Extended battery operation and quick wake-up time are important features in mobile consumer electronic devices. When a PLL generates the system clock, acquisition time can consume a significant portion of a sleep cycle, wasting energy that could provide useful processing. This paper presents a PLL architecture that improves lock time by at least an order of magnitude compared to an existing PLL.