Y. Sasago, H. Kurata, T. Arigane, K. Otsuga, T. Kobayashi, Y. Ikeda, T. Fukumura, S. Narumi, A. Sato, T. Terauchi, M. Shimizu, S. Noda, K. Kozakai, O. Tsuchiya, K. Furusawa
{"title":"90纳米节点多级AG-AND型闪存,单元大小为2 F/sup 2/ bit,编程吞吐量为10 MB/s","authors":"Y. Sasago, H. Kurata, T. Arigane, K. Otsuga, T. Kobayashi, Y. Ikeda, T. Fukumura, S. Narumi, A. Sato, T. Terauchi, M. Shimizu, S. Noda, K. Kozakai, O. Tsuchiya, K. Furusawa","doi":"10.1109/IEDM.2003.1269406","DOIUrl":null,"url":null,"abstract":"The first true 2-F/sup 2//bit flash cell with a programming throughput of 10 MB/s was developed. In this cell, diffusion-layer local bit lines of an assist-gate AND-type flash are replaced by inversion-layer ones under assist gates. The bit-line pitch is thus reduced to 2 F. A drain-disturbance-free and soft-write-free flash cell was produced by means of a new diffusion-layer-less technology. Source-side injection programming is applicable to the new flash cell; therefore, the cell programming time is reduced to 1 /spl mu/s. The smallest memory cell (0.0162 /spl mu/m/sup 2//bit) achieved to date was accomplished by using a 90-nm technology node and applying multi-level cell technology.","PeriodicalId":344286,"journal":{"name":"IEEE International Electron Devices Meeting 2003","volume":"31 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":"{\"title\":\"90-nm-node multi-level AG-AND type flash memory with cell size of true 2 F/sup 2//bit and programming throughput of 10 MB/s\",\"authors\":\"Y. Sasago, H. Kurata, T. Arigane, K. Otsuga, T. Kobayashi, Y. Ikeda, T. Fukumura, S. Narumi, A. Sato, T. Terauchi, M. Shimizu, S. Noda, K. Kozakai, O. Tsuchiya, K. Furusawa\",\"doi\":\"10.1109/IEDM.2003.1269406\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The first true 2-F/sup 2//bit flash cell with a programming throughput of 10 MB/s was developed. In this cell, diffusion-layer local bit lines of an assist-gate AND-type flash are replaced by inversion-layer ones under assist gates. The bit-line pitch is thus reduced to 2 F. A drain-disturbance-free and soft-write-free flash cell was produced by means of a new diffusion-layer-less technology. Source-side injection programming is applicable to the new flash cell; therefore, the cell programming time is reduced to 1 /spl mu/s. The smallest memory cell (0.0162 /spl mu/m/sup 2//bit) achieved to date was accomplished by using a 90-nm technology node and applying multi-level cell technology.\",\"PeriodicalId\":344286,\"journal\":{\"name\":\"IEEE International Electron Devices Meeting 2003\",\"volume\":\"31 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2003-12-08\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"8\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE International Electron Devices Meeting 2003\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IEDM.2003.1269406\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE International Electron Devices Meeting 2003","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.2003.1269406","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 8
摘要
开发了第一个真正的2- f /sup 2//bit闪存单元,编程吞吐量为10 MB/s。在该单元中,辅助门与型闪存的扩散层局部位线被辅助门下的反转层位线所取代。位线间距因此减少到2f。采用一种新的无扩散层技术制备了一种无漏失干扰、无软写的闪存电池。源端注入编程适用于新的闪存单元;因此,单元编程时间减少到1 /spl mu/s。迄今为止,最小的存储单元(0.0162 /spl mu/m/sup 2//bit)是通过采用90nm技术节点和多级存储单元技术实现的。
90-nm-node multi-level AG-AND type flash memory with cell size of true 2 F/sup 2//bit and programming throughput of 10 MB/s
The first true 2-F/sup 2//bit flash cell with a programming throughput of 10 MB/s was developed. In this cell, diffusion-layer local bit lines of an assist-gate AND-type flash are replaced by inversion-layer ones under assist gates. The bit-line pitch is thus reduced to 2 F. A drain-disturbance-free and soft-write-free flash cell was produced by means of a new diffusion-layer-less technology. Source-side injection programming is applicable to the new flash cell; therefore, the cell programming time is reduced to 1 /spl mu/s. The smallest memory cell (0.0162 /spl mu/m/sup 2//bit) achieved to date was accomplished by using a 90-nm technology node and applying multi-level cell technology.