{"title":"基于多模冗余的容错收缩阵列的系统生成","authors":"M. Kaneko, H. Miyauchi","doi":"10.1109/ASPDAC.1995.486410","DOIUrl":null,"url":null,"abstract":"A systematic procedure to configure fault-tolerant systolic arrays based on Multiplicated Multiple Modular Redundancy is proposed. Resultant systolic arrays tolerate failures not only on processing elements but also on communication links. While, to guarantee the fault-tolerance on communication links, sophisticated connection schemes between processing elements are needed in general, link complexity is reduced by optimizing the redundant operation scheme.","PeriodicalId":119232,"journal":{"name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1995-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A systematic generation of fault tolerant systolic arrays based on multiplicated multiple modular redundancy\",\"authors\":\"M. Kaneko, H. Miyauchi\",\"doi\":\"10.1109/ASPDAC.1995.486410\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A systematic procedure to configure fault-tolerant systolic arrays based on Multiplicated Multiple Modular Redundancy is proposed. Resultant systolic arrays tolerate failures not only on processing elements but also on communication links. While, to guarantee the fault-tolerance on communication links, sophisticated connection schemes between processing elements are needed in general, link complexity is reduced by optimizing the redundant operation scheme.\",\"PeriodicalId\":119232,\"journal\":{\"name\":\"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1995-08-29\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASPDAC.1995.486410\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASPDAC.1995.486410","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A systematic generation of fault tolerant systolic arrays based on multiplicated multiple modular redundancy
A systematic procedure to configure fault-tolerant systolic arrays based on Multiplicated Multiple Modular Redundancy is proposed. Resultant systolic arrays tolerate failures not only on processing elements but also on communication links. While, to guarantee the fault-tolerance on communication links, sophisticated connection schemes between processing elements are needed in general, link complexity is reduced by optimizing the redundant operation scheme.
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