{"title":"专用处理器加速DSP功能","authors":"G. Landers","doi":"10.1109/ELECTR.1996.501227","DOIUrl":null,"url":null,"abstract":"A new class of arithmetic datapath processors are available in either device or embedded form. These reconfigurable arithmetic datapath (RADTM) devices offer reconfigurablilty of FPGAs with the performance of algorithm specific silicon designs. The heart of the RAD architecture is a MacroSequencer. By programming the MacroSequencer to a specific algorithm, the hardware configures itself to that algorithm. Operations are performed concurrently in the pipelined structure. All programming, short term data storage and coefficients are stored within the MacroSequencer. The RAD MacroSequencer may be reconfigured to a new algorithm in as little as 25 ms. The RAD architecture is particularly suited to accelerating the performance of data stream algorithms.","PeriodicalId":119154,"journal":{"name":"Professional Program Proceedings. ELECTRO '96","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1996-04-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Special purpose processor speeds up DSP functions\",\"authors\":\"G. Landers\",\"doi\":\"10.1109/ELECTR.1996.501227\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A new class of arithmetic datapath processors are available in either device or embedded form. These reconfigurable arithmetic datapath (RADTM) devices offer reconfigurablilty of FPGAs with the performance of algorithm specific silicon designs. The heart of the RAD architecture is a MacroSequencer. By programming the MacroSequencer to a specific algorithm, the hardware configures itself to that algorithm. Operations are performed concurrently in the pipelined structure. All programming, short term data storage and coefficients are stored within the MacroSequencer. The RAD MacroSequencer may be reconfigured to a new algorithm in as little as 25 ms. The RAD architecture is particularly suited to accelerating the performance of data stream algorithms.\",\"PeriodicalId\":119154,\"journal\":{\"name\":\"Professional Program Proceedings. ELECTRO '96\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1996-04-30\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Professional Program Proceedings. ELECTRO '96\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ELECTR.1996.501227\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Professional Program Proceedings. ELECTRO '96","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ELECTR.1996.501227","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A new class of arithmetic datapath processors are available in either device or embedded form. These reconfigurable arithmetic datapath (RADTM) devices offer reconfigurablilty of FPGAs with the performance of algorithm specific silicon designs. The heart of the RAD architecture is a MacroSequencer. By programming the MacroSequencer to a specific algorithm, the hardware configures itself to that algorithm. Operations are performed concurrently in the pipelined structure. All programming, short term data storage and coefficients are stored within the MacroSequencer. The RAD MacroSequencer may be reconfigured to a new algorithm in as little as 25 ms. The RAD architecture is particularly suited to accelerating the performance of data stream algorithms.
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