模集{22n+1-1,22n,2n-1}的残二变换器

K. Gbolagade, R. Chaves, L. Sousa, S. Cotofana
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引用次数: 10

摘要

本文针对模集{22n+1 -1,22n,2n -1}提出了两种无记忆转换器。首先,我们提出了一个新的反向变换器,它是纯加法器的基础上,利用传统的中国剩余定理(CRT)。其次,由于所提出的基于CRT的结构不能覆盖整个动态范围,因此提出了基于混合基数转换(MRC)的第二种转换器,该转换器覆盖整个动态范围。基于CRT的变换器在面积和延迟方面都优于基于MRC的变换器。与目前最先进的变换器相比,本文提出的基于CRT的方案在面积成本和转换延迟方面都优于现有的变换器。实验结果支持了理论评价,并在标准电池0.13-µm CMOS工艺上进行了估计。这些实验结果表明,平均而言,在相同的动态范围内,与现有的基于MRC的转换器相比,所提出的基于CRT的转换器实现了约23%的延迟减少,面积减少超过3%。此外,与现有的基于CRT的转换器相比,所提出的基于CRT的转换器速度约快6%,面积减少约4%。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Residue-to-binary converters for the moduli set {22n+1-1,22n,2n-1}
In this paper, we propose two memoryless converters for the moduli set {22n+1 -1,22n,2n -1}. First, we propose a novel reverse converter, which is purely adder based, using the traditional Chinese Remainder Theorem (CRT). Second, due to the fact that the proposed CRT based structure does not cover the entire dynamic range, a second converter, which covers the entire dynamic range based on Mixed Radix Conversion (MRC), is proposed. The CRT based converter outperforms the MRC based converter both in terms of area and delay. In comparison with related best known state of the art converters, they are all outperformed by the proposed CRT based scheme in terms of both area cost and conversion delay. The theoretical evaluation is supported by the experimental results, which are estimated on a Standard Cell 0.13-µm CMOS technology. These experimental results indicate that, on average, for the same dynamic range, the proposed CRT based converter achieves about 23% delay reduction with more than 3% area reduction, when compared to the existing state of the art MRC based converter. Additionally, the proposed CRT based converter is about 6% faster with about 4% area reduction when compared with the existing CRT based converter.
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