{"title":"基于ota的全差分对称轨对轨切换缓冲器","authors":"V. Stornelli, G. Ferri, A. De Marcellis","doi":"10.1109/RME.2007.4401817","DOIUrl":null,"url":null,"abstract":"A CMOS low-voltage low-power switched OTA, optimized for its buffer configuration, suitable for both many portable applications and as input stage in digital architectures, is here presented. The circuit is a fully differential topology based on a symmetrical OTA featuring a rail-to-rail input and a reduced CMRR. It has been designed in a standard CMOS 0.35 mum technology and operates at 2V single supply voltage, showing a maximum power consumption of about 560 muW. Simulation results have confirmed the validity of the proposed architecture and have shown a -85dB THD for 100 kHz clock frequency, when a single tone input with lVpp amplitude at 10 kHz is applied.","PeriodicalId":118230,"journal":{"name":"2007 Ph.D Research in Microelectronics and Electronics Conference","volume":"6 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-07-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"A fully-differential symmetrical OTA-based rail-to-rail switched buffer\",\"authors\":\"V. Stornelli, G. Ferri, A. De Marcellis\",\"doi\":\"10.1109/RME.2007.4401817\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A CMOS low-voltage low-power switched OTA, optimized for its buffer configuration, suitable for both many portable applications and as input stage in digital architectures, is here presented. The circuit is a fully differential topology based on a symmetrical OTA featuring a rail-to-rail input and a reduced CMRR. It has been designed in a standard CMOS 0.35 mum technology and operates at 2V single supply voltage, showing a maximum power consumption of about 560 muW. Simulation results have confirmed the validity of the proposed architecture and have shown a -85dB THD for 100 kHz clock frequency, when a single tone input with lVpp amplitude at 10 kHz is applied.\",\"PeriodicalId\":118230,\"journal\":{\"name\":\"2007 Ph.D Research in Microelectronics and Electronics Conference\",\"volume\":\"6 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2007-07-02\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2007 Ph.D Research in Microelectronics and Electronics Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/RME.2007.4401817\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 Ph.D Research in Microelectronics and Electronics Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/RME.2007.4401817","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A fully-differential symmetrical OTA-based rail-to-rail switched buffer
A CMOS low-voltage low-power switched OTA, optimized for its buffer configuration, suitable for both many portable applications and as input stage in digital architectures, is here presented. The circuit is a fully differential topology based on a symmetrical OTA featuring a rail-to-rail input and a reduced CMRR. It has been designed in a standard CMOS 0.35 mum technology and operates at 2V single supply voltage, showing a maximum power consumption of about 560 muW. Simulation results have confirmed the validity of the proposed architecture and have shown a -85dB THD for 100 kHz clock frequency, when a single tone input with lVpp amplitude at 10 kHz is applied.
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