1090 MHz SSR接收和精确TOA估计站的FPGA实现

Stephan Bernhart, G. Hofbauer, Ulrich Feichter, E. Leitgeb
{"title":"1090 MHz SSR接收和精确TOA估计站的FPGA实现","authors":"Stephan Bernhart, G. Hofbauer, Ulrich Feichter, E. Leitgeb","doi":"10.1109/ConTEL.2015.7231201","DOIUrl":null,"url":null,"abstract":"In this article the first complete 1,090 MHz SSR receiving and precision time of arrival (TOA) estimation station field programmable gate array (FPGA) implementation and its analog electronic front-end is presented. The station is designed for local area multilateration (LAM), wide area multilateration (WAM) and automatic dependent surveillance-broadcast (ADS-B) systems. Furthermore it's fully international civil aviation organization (ICAO) annex X volume IV [1], ED-117 [2] and ED-142 [3] compliant. The station consists principally of an antenna, an analog front-end, an analog-to-digital converter (ADC), a FPGA and a system-on-chip (SoC) microcomputer. The secondary surveillance radar (SSR) signals are received with a low loss half-wave vertical dipole antenna, amplified and then down-converted with the analog front-end, digitalized with the ADCs and finally demodulated, decoded and TOA estimated with the FPGA implementation. The microcomputer's scope is to emit the decoded and TOA estimated SSR signals and its monitoring information over the network to the central processing station (CPS). To achieve high position accuracy the system's clock reference is locked to an oven controlled crystal oscillator (OCXO) with an optional global position system (GPS) correction. The presented architecture is capable of time stamping with a resolution of 40 ps and an RMS accuracy of 1.5 ns, which corresponds to a distance accuracy of 0.3 m.","PeriodicalId":134613,"journal":{"name":"2015 13th International Conference on Telecommunications (ConTEL)","volume":"69 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-07-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"FPGA implementation of a 1,090 MHz SSR receiving and precision TOA estimation station\",\"authors\":\"Stephan Bernhart, G. Hofbauer, Ulrich Feichter, E. Leitgeb\",\"doi\":\"10.1109/ConTEL.2015.7231201\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this article the first complete 1,090 MHz SSR receiving and precision time of arrival (TOA) estimation station field programmable gate array (FPGA) implementation and its analog electronic front-end is presented. The station is designed for local area multilateration (LAM), wide area multilateration (WAM) and automatic dependent surveillance-broadcast (ADS-B) systems. Furthermore it's fully international civil aviation organization (ICAO) annex X volume IV [1], ED-117 [2] and ED-142 [3] compliant. The station consists principally of an antenna, an analog front-end, an analog-to-digital converter (ADC), a FPGA and a system-on-chip (SoC) microcomputer. The secondary surveillance radar (SSR) signals are received with a low loss half-wave vertical dipole antenna, amplified and then down-converted with the analog front-end, digitalized with the ADCs and finally demodulated, decoded and TOA estimated with the FPGA implementation. The microcomputer's scope is to emit the decoded and TOA estimated SSR signals and its monitoring information over the network to the central processing station (CPS). To achieve high position accuracy the system's clock reference is locked to an oven controlled crystal oscillator (OCXO) with an optional global position system (GPS) correction. The presented architecture is capable of time stamping with a resolution of 40 ps and an RMS accuracy of 1.5 ns, which corresponds to a distance accuracy of 0.3 m.\",\"PeriodicalId\":134613,\"journal\":{\"name\":\"2015 13th International Conference on Telecommunications (ConTEL)\",\"volume\":\"69 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2015-07-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2015 13th International Conference on Telecommunications (ConTEL)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ConTEL.2015.7231201\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 13th International Conference on Telecommunications (ConTEL)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ConTEL.2015.7231201","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0

摘要

本文介绍了首个完整的1090mhz SSR接收与精确到达时间(TOA)估计站的现场可编程门阵列(FPGA)实现及其模拟电子前端。该站设计用于局部区域复用(LAM)、广域复用(WAM)和自动相关监视广播(ADS-B)系统。此外,它完全符合国际民用航空组织(ICAO)附件X卷四[1]、ED-117[2]和ED-142[3]的要求。该站主要由天线、模拟前端、模数转换器(ADC)、FPGA和片上系统(SoC)微型计算机组成。利用低损耗半波垂直偶极子天线接收二次监视雷达(SSR)信号,通过模拟前端进行放大后的下变频,通过adc进行数字化,最后通过FPGA实现解调、解码和TOA估计。微型计算机的工作范围是通过网络向中央处理站(CPS)发射解码和TOA估计的SSR信号及其监测信息。为了实现高位置精度,系统的时钟参考被锁定到一个具有可选全球定位系统(GPS)校正的烤箱控制晶体振荡器(OCXO)。所提出的架构能够以40 ps的分辨率和1.5 ns的均方根精度进行时间戳,这相当于0.3 m的距离精度。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
FPGA implementation of a 1,090 MHz SSR receiving and precision TOA estimation station
In this article the first complete 1,090 MHz SSR receiving and precision time of arrival (TOA) estimation station field programmable gate array (FPGA) implementation and its analog electronic front-end is presented. The station is designed for local area multilateration (LAM), wide area multilateration (WAM) and automatic dependent surveillance-broadcast (ADS-B) systems. Furthermore it's fully international civil aviation organization (ICAO) annex X volume IV [1], ED-117 [2] and ED-142 [3] compliant. The station consists principally of an antenna, an analog front-end, an analog-to-digital converter (ADC), a FPGA and a system-on-chip (SoC) microcomputer. The secondary surveillance radar (SSR) signals are received with a low loss half-wave vertical dipole antenna, amplified and then down-converted with the analog front-end, digitalized with the ADCs and finally demodulated, decoded and TOA estimated with the FPGA implementation. The microcomputer's scope is to emit the decoded and TOA estimated SSR signals and its monitoring information over the network to the central processing station (CPS). To achieve high position accuracy the system's clock reference is locked to an oven controlled crystal oscillator (OCXO) with an optional global position system (GPS) correction. The presented architecture is capable of time stamping with a resolution of 40 ps and an RMS accuracy of 1.5 ns, which corresponds to a distance accuracy of 0.3 m.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术官方微信