Performance Of A Convolutionally Coded Chip Combiner DS Receiver In Pulsed Noise And CW Interference

The performance of a chip combiner DS/BPSK receiver is analysed by means of an extensive Monte-Carlo computer simulation in an AWGN channel, in pulsed WGN and in CW interference using BPSK modulation and an optimum convolutional code of constraint length 7 and code rate 1/2. It is assumed that an interleaver will randomize error bursts. The receiver employs a soft decision Viterbi decoder and a chip combiner interference estimation circuit. The receiver structure eliminates the need for a fast-acting AGC circuit and instead it is assumed that the AGC will remain constant under an interference pulse. The chip combiner DS receiver proved to be robust in the pulsed interference. The optimum erasure level can be determined by simulation if the interference scenario is known. Otherwise good compromises can be determined.