一个1.5 V 2.4/2.9 mW 79/50 dB DR /spl Sigma//spl Delta/调制器，用于GSM/WCDMA，数字处理速度为0.13 /spl mu/m

2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315) Pub Date : 2002-08-07 DOI:10.1109/ISSCC.2002.993054

G. Gómez, B. Haroun

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引用次数: 7

摘要

用于低功耗多标准无线接收机的2/sup和/ order多级/spl Sigma//spl Delta/ A/D转换器，采用单poly 0.13 /spl mu/m数字CMOS工艺，具有79/50 dB动态范围，适用于GSM/WCDMA。0.2 mm/sup 2/芯片在1.5 V时消耗2.4/2.9 mW。

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A 1.5 V 2.4/2.9 mW 79/50 dB DR /spl Sigma//spl Delta/ modulator for GSM/WCDMA in a 0.13 /spl mu/m digital process

A 2/sup nd/ order multi-level /spl Sigma//spl Delta/ A/D converter for low-power multi-standard wireless receivers, in a single-poly 0.13 /spl mu/m digital CMOS process, has 79/50 dB dynamic range for GSM/WCDMA. The 0.2 mm/sup 2/ chip consumes 2.4/2.9 mW at 1.5 V.

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2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)

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