{"title":"发射机结构采用数字生成射频信号","authors":"J. Rode, J. Hinrichs, P. Asbeck","doi":"10.1109/RAWCON.2003.1227938","DOIUrl":null,"url":null,"abstract":"This paper describes architecture for a CDMA RF transmitter implemented in digital CMOS. The functions of up-conversion and filtering are carried out in the digital domain. A band-pass delta-sigma modulator is used to produce a one-bit output containing the desired analog signal, which is then fed to switching-mode power amplifier. Issues for the digital logic implementation to facilitate proper modulator operation at the required high clock rates (>3.3 GHz) are discussed in detail.","PeriodicalId":177645,"journal":{"name":"Radio and Wireless Conference, 2003. RAWCON '03. Proceedings","volume":"222 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2003-09-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"22","resultStr":"{\"title\":\"Transmitter architecture using digital generation of RF signals\",\"authors\":\"J. Rode, J. Hinrichs, P. Asbeck\",\"doi\":\"10.1109/RAWCON.2003.1227938\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper describes architecture for a CDMA RF transmitter implemented in digital CMOS. The functions of up-conversion and filtering are carried out in the digital domain. A band-pass delta-sigma modulator is used to produce a one-bit output containing the desired analog signal, which is then fed to switching-mode power amplifier. Issues for the digital logic implementation to facilitate proper modulator operation at the required high clock rates (>3.3 GHz) are discussed in detail.\",\"PeriodicalId\":177645,\"journal\":{\"name\":\"Radio and Wireless Conference, 2003. RAWCON '03. Proceedings\",\"volume\":\"222 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2003-09-08\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"22\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Radio and Wireless Conference, 2003. RAWCON '03. Proceedings\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/RAWCON.2003.1227938\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Radio and Wireless Conference, 2003. RAWCON '03. Proceedings","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/RAWCON.2003.1227938","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Transmitter architecture using digital generation of RF signals
This paper describes architecture for a CDMA RF transmitter implemented in digital CMOS. The functions of up-conversion and filtering are carried out in the digital domain. A band-pass delta-sigma modulator is used to produce a one-bit output containing the desired analog signal, which is then fed to switching-mode power amplifier. Issues for the digital logic implementation to facilitate proper modulator operation at the required high clock rates (>3.3 GHz) are discussed in detail.
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