Implementation of a pipeline division-free MMSE MIMO detector that support soft-input and soft-output

This paper mainly addresses on MIMO decoder implementations that support iterative detecting and decoding. Based on MMSE-PIC algorithm, we present architectures for optimized matrix inverse and LLR caculation that are division free. We also present a parallel complex matrix QR decomposition scheme to develop a pipeline VLSI achitecture. ASIC realization of this architecture for both 2 × 2 and 4 × 4 configuration are also finished, the synthesis result shows that peak throughput of 4 × 4 design reachs 1.43Gbps at the area cost of 797k logic gates. The 2 × 2 design also have a relative high hardware effeciency compared with the state of art implementation.