一个70和210 GHz的LO发生器在65nm CMOS

C. Bryant, J. Lindstrand, H. Sjoland, M. Tormanen
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引用次数: 1

摘要

提出了一种工作在70GHz和210GHz的CMOS低电压发生器,采用三倍频技术。交叉耦合NMOS压控振荡器与单平衡混频器一起使用,以实现低相位噪声。该芯片在70GHz频段的单端输出功率为-15dBm,调谐范围为6.54%,电源为1.2V,功耗为7.2mW。在载波频率为73.8GHz的10MHz频偏下,测得相位噪声为-113.2dBc/Hz。这产生的相位噪声值FOM为181.8dB,考虑到调谐范围,FOM为178dB。通过使用该技术,在210GHz频段内既不会降低FOM,也不会降低FOM,因为功耗和调谐范围都得到了保持。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A 70 and 210 GHz LO generator in 65nm CMOS
A CMOS LO-Generator operating at 70GHz and 210GHz by the use of a frequency tripling technique is presented. A cross-coupled NMOS VCO is used together with a single-balanced mixer to achieve low phase-noise. The chip measures a single-ended output power of -15dBm in the 70GHz band, with 6.54% tuning range, from a 1.2V supply while consuming 7.2mW. A phase-noise of -113.2dBc/Hz is measured at 10MHz frequency offset from a carrier frequency of 73.8GHz. This yields a phase noise figure of merit, FOM, of 181.8dB, and with the tuning range taken into account, a FOMT of 178dB. By using this technique neither FOM nor FOMT are degraded in the 210GHz band since both power consumption and tuning range are maintained.
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