Design Optimization, Fabrication And Testing Of A Capacitive Silicon Accelerometer Using An Soi Approach

In this paper the design, fabrication and testing of the capacitive micro accelerometer with Silicon On Insulator (SOI) approach is presented. The beam location with respect to a rectangular mass is optimized, using finite element analysis (FEM) to minimize cross axis sensitivity. It is demonstrated that a simple KOH etching with the addition of the tert-butanol can be easily adopted to fabricate the accelerometer structure without any convex undercutting effects. The devices are tested by electrostatic actuation.