Fast mixed-mode PLL simulation using behavioral baseband models of voltage-controlled oscillators and frequency dividers

This article presents a new approach to fast mixed-mode simulation of phase-locked loops (PLLs) in time domain using Spice-like simulators and behavioral Verilog-A baseband (BB) models of voltage-controlled oscillators (VCO) and frequency dividers (FD). Other PLL blocks like phase-frequency detectors (PFD), charge pumps (CP), and loop filters (LP) can be transistor level and/or behavioral models. The use of both VCO and FD BB models in mixed-mode test bench allows fast PLL simulation and optimization of modern sophisticated PFD and CP blocks on transistor level with speedups of about 2–3 orders of magnitude.