基于TiO2>/sub>忆阻器的存储器阵列产率最大化

Marwa Abdallah, H. Mostafa, Mohamed Fathy
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引用次数: 3

摘要

当惠普实验室在2008年开发出第一个真正的忆阻器器件时,缺失的第四个无源电路元件忆阻器引起了极大的关注。由于忆阻器是在纳米尺度几何尺寸上制造的,其工艺变化难以控制,因此其制造面临着各种挑战。工艺变化导致记忆电阻器的实际电学性能偏离期望值。这种偏差导致了成品率的降低,特别是在基于忆阻器的存储器设计中。因此,了解和表征工艺变化对忆阻器性能和良率的影响,并尝试最大限度地提高基于忆阻器的存储阵列的良率是非常重要的。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Yield maximization of TiO2>/sub> memristor-based memory arrays
The missing fourth passive circuit element, the memristor, attracted a great attention when HP labs developed the first real memristor device in 2008. The memristor manufacturing is facing various challenges due to the difficulty to control its process variation, as it is fabricated at nano-scale geometry's size. Process variation result in deviating the actual electrical behavior of memristors from the desired values. This deviation results in reducing the yield especially in the memristor-based memory design. Therefore, it is very important to understand and characterize the impact of process variation on memristor performance and yield and attempt to maximize the yield of the memristor-based memory arrays.
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