{"title":"在Xilinx系统生成器中使用基数排序亭算法的多速率FIR滤波器","authors":"Zulfiqar Ali, Sania Syed, Syed Tahir Hussain Shah, Wesam Khalil, Muhammad Ayaz","doi":"10.1109/ICETECC56662.2022.10069905","DOIUrl":null,"url":null,"abstract":"Multirate Finite Impulse response (FIR) filters are extensively utilised in digital signal processing in which different filter parts operate at different rates. It has applications in communication transmitters and receivers. Multirate FIR filters when implemented use multipliers and accumulators. There are various types of multiplier structure algorithms and their variations such as Combinational multiplier, Wallace Tree multiplier, Array multiplier and Sequential multiplier and Booth multiplier. Booth multipliers reduces the resulting number of partial products generated as a result of multiplication of two binary numbers. Mutlirate FIR filter has been implemented using with radix-2, 4, 8, 16 and 32 booth recoding algorithm. Multirate 23-tap FIR filter has been implemented using Xilinx System Generator 14.7 which is compatible with MATLAB 2013b. Booth multipliers using different radix sort has been done using Verilog in Xilinx 14.7 and then the synthesized code is imported to Xilinx system generator (MATLAB). The concept of booth multipliers has been incorporated with Radix-4 based booth encoding multiplier performing better compared to other radices in terms of Slices, LUTs, DSP48, IOBs utilization and an Error reduction of about 0.00197%.","PeriodicalId":364463,"journal":{"name":"2022 International Conference on Emerging Technologies in Electronics, Computing and Communication (ICETECC)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2022-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Multirate FIR Filter Using Radix Sort Booth Algorithm In Xilinx System Generator\",\"authors\":\"Zulfiqar Ali, Sania Syed, Syed Tahir Hussain Shah, Wesam Khalil, Muhammad Ayaz\",\"doi\":\"10.1109/ICETECC56662.2022.10069905\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Multirate Finite Impulse response (FIR) filters are extensively utilised in digital signal processing in which different filter parts operate at different rates. It has applications in communication transmitters and receivers. Multirate FIR filters when implemented use multipliers and accumulators. There are various types of multiplier structure algorithms and their variations such as Combinational multiplier, Wallace Tree multiplier, Array multiplier and Sequential multiplier and Booth multiplier. Booth multipliers reduces the resulting number of partial products generated as a result of multiplication of two binary numbers. Mutlirate FIR filter has been implemented using with radix-2, 4, 8, 16 and 32 booth recoding algorithm. Multirate 23-tap FIR filter has been implemented using Xilinx System Generator 14.7 which is compatible with MATLAB 2013b. Booth multipliers using different radix sort has been done using Verilog in Xilinx 14.7 and then the synthesized code is imported to Xilinx system generator (MATLAB). The concept of booth multipliers has been incorporated with Radix-4 based booth encoding multiplier performing better compared to other radices in terms of Slices, LUTs, DSP48, IOBs utilization and an Error reduction of about 0.00197%.\",\"PeriodicalId\":364463,\"journal\":{\"name\":\"2022 International Conference on Emerging Technologies in Electronics, Computing and Communication (ICETECC)\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2022-12-07\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2022 International Conference on Emerging Technologies in Electronics, Computing and Communication (ICETECC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICETECC56662.2022.10069905\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 International Conference on Emerging Technologies in Electronics, Computing and Communication (ICETECC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICETECC56662.2022.10069905","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
摘要
多速率有限脉冲响应(FIR)滤波器广泛应用于数字信号处理中,其中不同的滤波器部分以不同的速率工作。它在通信发射机和接收机中都有应用。多速率FIR滤波器在实现时使用乘法器和累加器。乘法器结构算法有多种类型及其变体,如组合乘法器、华莱士树乘法器、阵列乘法器、顺序乘法器和布斯乘法器。布斯乘法器减少了由于两个二进制数相乘而产生的部分乘积的结果数。采用基数2、4、8、16和32摊位编码算法实现了多倍FIR滤波器。采用与MATLAB 2013b兼容的Xilinx System Generator 14.7实现了多速率23分岔FIR滤波器。在Xilinx 14.7中使用Verilog完成了不同基数排序的Booth乘法器,然后将合成代码导入到Xilinx系统生成器(MATLAB)中。展台乘法器的概念与基于基数4的展台编码乘法器相结合,在切片、lut、DSP48、IOBs利用率方面比其他基数表现更好,误差减少约0.00197%。
Multirate FIR Filter Using Radix Sort Booth Algorithm In Xilinx System Generator
Multirate Finite Impulse response (FIR) filters are extensively utilised in digital signal processing in which different filter parts operate at different rates. It has applications in communication transmitters and receivers. Multirate FIR filters when implemented use multipliers and accumulators. There are various types of multiplier structure algorithms and their variations such as Combinational multiplier, Wallace Tree multiplier, Array multiplier and Sequential multiplier and Booth multiplier. Booth multipliers reduces the resulting number of partial products generated as a result of multiplication of two binary numbers. Mutlirate FIR filter has been implemented using with radix-2, 4, 8, 16 and 32 booth recoding algorithm. Multirate 23-tap FIR filter has been implemented using Xilinx System Generator 14.7 which is compatible with MATLAB 2013b. Booth multipliers using different radix sort has been done using Verilog in Xilinx 14.7 and then the synthesized code is imported to Xilinx system generator (MATLAB). The concept of booth multipliers has been incorporated with Radix-4 based booth encoding multiplier performing better compared to other radices in terms of Slices, LUTs, DSP48, IOBs utilization and an Error reduction of about 0.00197%.