Development and demonstration of equivalent material characteristics for microbump arrays utilized in failure estimation of chip-on-chip packaging

To meet the requirements of electronic devices having high operated speed, multi-functions, and a low form factor, a great classic shift of the system integration composed of heterogeneous and homogenous substances from two-dimensional (2D) to 2.5D or even 3D integration is a promising solution while a physical limit of nano-scaled transistors and the bottlenecks emerge of related fabricated technologies are confronted. To realize the foregoing architectures of 3D-ICs packaging, the interconnects, composed of through silicon via (TSV) and microbumps, have attracted a lot of attentions due to high density connections among stacked chips can be vertically achieved. However, as the layout arrangements of microbump arrays are taken into account, because of numerous microbumps with complicated compositions and a significant dimensional mismatch among them, the failure location and precise reliability estimation of a whole packaging structure are difficult to acquire by the simulated predictions directly. To resolve this problem, the methodology of equivalent material characteristics for microbump arrays extracted from finite element analysis (FEA) by using the way of usual bulk material tests is proposed in this study. To demonstrate the feasibility of above-mentioned approach, a testing vehicle of chip-on-chip packaging with wafer level underfills (WLUFs) is utilized to explore the applied influence of internal microbump arrays with equivalent material properties on the magnitude and contour of stresses at the critical locations where the detailed configurations of microbumps are still needed to construct in FEA under the loading of temperature cycling test. In addition, the present approach for equivalent material properties of microbumps combined with a global/local sub-modeling technique is also implemented and discussed, separately. Under the supposition of that the lead-free solder within a microbump is completely transferred to Ni3Sn4 intermetallic compound (IMC), the maximum principal stress of IMC layer based on the failure mode of brittle matter is used to judge the numerical convergence of FEA. The results indicate that at least four rows of real micrbumps originated from the outermost array edge of packaging structure are required to maintain the numerical accuracy as compared with the consequence obtained by a fully constructed simulated model. Moreover, it is found that a small deviation of 5 % in stress magnitude by using a sub-modeling technique can be managed when a distance of 60 μm between the edge of local model and concerned microbump is taken into account.