FPGA Hardware Co-Simulation of a Stream Cipher Image Cryptosystem based on Fixed-Point Chaotic Map

As communication technology advances, the security and real-time exchange of images have become a primary concern. Chaotic systems exhibit interesting features for image cryptography, and their hardware implementation is a challenging task to accelerate the cryptosystem. This paper proposes an FPGA implementation of a robust Fixed-Point Cubic-Tent Map Pseudorandom Bit Generator (FPCTM-PRBG) image cryptosystem for a real-time application based on the Xilinx System Generator (XSG). We designed the new FPCTM-PRBG using XSG to produce the keystream sequence. Then, the encryption is performed using the XOR operation between the plain image and the FPCTM-PRBG stream sequence to get the cipher image. The decryption process is executed by XORing the encrypted image sequence with the FPCTM-PRBG. The algorithm is designed, implemented, and validated using Vivado/System Generator tool through the FPGA-ZC702 evaluation board. The performance of the proposed cryptosystem is evaluated based on statistical analysis, differential analysis, PSNR, and image entropy. Also, hardware co-simulation is performed to test the image encryption system in real-time using a generated JTAG co-simulation system. Thus, the architecture of the proposed cryptosystem is flexible due to the FPGA design. The obtained results prove the higher performance and high-security level of the proposed cryptosystem with low power consumption (238 mW) and a reduced encryption time.