A High-Performance Fault Diagnosis Approach for the AES SubBytes Utilizing Mixed Bases

The Sub Bytes (S-boxes) is the only non-linear transformation in the encryption of the Advanced Encryption Standard (AES), occupying more than half of its hardware implementation resources. One important required aspect of the hardware architectures of the S-boxes is the reliability of their implementations. This can be compromised by occurrence of internal faults or intrusion of the attackers. In this paper, we present a high-speed architecture for the S-boxes constructed using mixed bases to counteract these internal/malicious faults. Although using polynomial and normal bases for the S-boxes has been studied extensively, using mixed bases has just been considered very recently in CHES 2010. In the proposed fault detection scheme of this paper, we present formulations for multi-bit parities for the S-boxes using mixed bases. Then, these formulations are utilized in our error simulations and it is shown that the presented architecture reaches very high error coverage. Through our ASIC syntheses utilizing a 65-nm CMOS technology, we show that with comparable hardware complexity, the efficiency of the presented reliable architecture (without sub-pipelining) reaches around $5.02$ $\frac{Mbps}{\mu m^{2}}$, outperforming other fault detection schemes for composite field architectures.