V. V. D. Araujo, R. A. Hernandez, E. Simas, Amauri Oliveira, Wagner L. A. de Olivera
{"title":"专用硬件实现的高精度电能质量仪表","authors":"V. V. D. Araujo, R. A. Hernandez, E. Simas, Amauri Oliveira, Wagner L. A. de Olivera","doi":"10.1109/I2MTC.2015.7151300","DOIUrl":null,"url":null,"abstract":"Low power quality may cause serious problems in industrial, corporative and residential electrical networks. Among the most common problems one can mention the reduction of equipment lifetime, false activation of protection devices and electrical and thermal losses increase. Considering this, it is very important to monitor the power quality of a given facility. This paper describes the architecture of custom application-specific integrated circuit (ASIC) for power quality measurement. The digital signal processing measurements are based on IEC standards (61000-4-30, 61000-4-7, and 61000-4-15 class-A). The proposed Integrated Circuit (IC) supports poly-phase measuring for 7 channels with high precision estimation of parameters such as RMS value, crest factor, harmonics, interharmonics, total harmonics distortion, angle, unbalance, active power, apparent power, and instantaneous frequency. There is also a Real Time Clock (RTC) that enables system synchronization, predicted in the standards to perform phasor measurement. The main focus of this paper is describing the digital signal processing blocks of the proposed IC. The designed ASIC was produced using TowerJazz 180nm CMOS technology. Multiple clocks are used to reduce area (by optimizing single port memories), enable faster external communication, and reduce power consumption.","PeriodicalId":424006,"journal":{"name":"2015 IEEE International Instrumentation and Measurement Technology Conference (I2MTC) Proceedings","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-05-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"Dedicated hardware implementation of a high precision power quality meter\",\"authors\":\"V. V. D. Araujo, R. A. Hernandez, E. Simas, Amauri Oliveira, Wagner L. A. de Olivera\",\"doi\":\"10.1109/I2MTC.2015.7151300\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Low power quality may cause serious problems in industrial, corporative and residential electrical networks. Among the most common problems one can mention the reduction of equipment lifetime, false activation of protection devices and electrical and thermal losses increase. Considering this, it is very important to monitor the power quality of a given facility. This paper describes the architecture of custom application-specific integrated circuit (ASIC) for power quality measurement. The digital signal processing measurements are based on IEC standards (61000-4-30, 61000-4-7, and 61000-4-15 class-A). The proposed Integrated Circuit (IC) supports poly-phase measuring for 7 channels with high precision estimation of parameters such as RMS value, crest factor, harmonics, interharmonics, total harmonics distortion, angle, unbalance, active power, apparent power, and instantaneous frequency. There is also a Real Time Clock (RTC) that enables system synchronization, predicted in the standards to perform phasor measurement. The main focus of this paper is describing the digital signal processing blocks of the proposed IC. The designed ASIC was produced using TowerJazz 180nm CMOS technology. Multiple clocks are used to reduce area (by optimizing single port memories), enable faster external communication, and reduce power consumption.\",\"PeriodicalId\":424006,\"journal\":{\"name\":\"2015 IEEE International Instrumentation and Measurement Technology Conference (I2MTC) Proceedings\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2015-05-11\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2015 IEEE International Instrumentation and Measurement Technology Conference (I2MTC) Proceedings\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/I2MTC.2015.7151300\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 IEEE International Instrumentation and Measurement Technology Conference (I2MTC) Proceedings","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/I2MTC.2015.7151300","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Dedicated hardware implementation of a high precision power quality meter
Low power quality may cause serious problems in industrial, corporative and residential electrical networks. Among the most common problems one can mention the reduction of equipment lifetime, false activation of protection devices and electrical and thermal losses increase. Considering this, it is very important to monitor the power quality of a given facility. This paper describes the architecture of custom application-specific integrated circuit (ASIC) for power quality measurement. The digital signal processing measurements are based on IEC standards (61000-4-30, 61000-4-7, and 61000-4-15 class-A). The proposed Integrated Circuit (IC) supports poly-phase measuring for 7 channels with high precision estimation of parameters such as RMS value, crest factor, harmonics, interharmonics, total harmonics distortion, angle, unbalance, active power, apparent power, and instantaneous frequency. There is also a Real Time Clock (RTC) that enables system synchronization, predicted in the standards to perform phasor measurement. The main focus of this paper is describing the digital signal processing blocks of the proposed IC. The designed ASIC was produced using TowerJazz 180nm CMOS technology. Multiple clocks are used to reduce area (by optimizing single port memories), enable faster external communication, and reduce power consumption.