Application of energy reduction techniques using niched pareto GA of energy analzyer for HPC applications

Energy consumption of High Performance Computing (HPC) architectures, on the path to exa-scale systems, is still a challenging problem among the HPC community owing to the technological issues, such as, power limitations of processor technologies, increased degree of parallelism (both in a node level and in a system level), and a hefty cost of communication which arises while executing applications on such architectures. In addition, the increased electrical billing and the other ensuing ecological hazards, including climate changes, have urged several researchers to focus much on framing solutions that address the energy consumption issues of future HPC systems. Reducing the energy consumption of HPC systems, however, is not an easy task due to its assorted nature of muddled up complicated issues that are tightly dependent on the performance of applications, the energy efficiency of hardware components, and the energy consumption of the compute center infrastructure. This paper presents Niched Pareto Genetic Algorithm (NPGA) based application of energy reduction techniques, namely, code version selection mechanism and compiler optimization switch selection mechanism, for HPC applications using Energy Analyzer tool. The proposed mechanism was tested with HPC applications, such as, MPI-C based HPCC benchmarks, Jacobi, PI, and matrix multiplication applications, on the HPCCLoud Research Laboratory of our premise. This paper could be of an interest to various researchers, namely, HPC application developers, performance analysis tool developers, environmentalist, and energy-aware hardware designers.