{"title":"紧凑的低压CMOS模拟分频器,采用四象限乘法器和偏置控制电路","authors":"I. Padilla-Cantoya","doi":"10.1109/MWSCAS.2012.6292067","DOIUrl":null,"url":null,"abstract":"A compact low-voltage analog divider is presented. The design is based on a four-quadrant multiplier and a differential transconductance amplifier as basic building blocks operating in voltage mode. A biasing control circuit to set the dc operational point that requires very few devices and offers continuous-time operation is included. Experimental results of a test chip in 0.5μm CMOS technology verify the proposed operation.","PeriodicalId":324891,"journal":{"name":"2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2012-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"Compact low-voltage CMOS analog divider using a four-quadrant multiplier and biasing control circuit\",\"authors\":\"I. Padilla-Cantoya\",\"doi\":\"10.1109/MWSCAS.2012.6292067\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A compact low-voltage analog divider is presented. The design is based on a four-quadrant multiplier and a differential transconductance amplifier as basic building blocks operating in voltage mode. A biasing control circuit to set the dc operational point that requires very few devices and offers continuous-time operation is included. Experimental results of a test chip in 0.5μm CMOS technology verify the proposed operation.\",\"PeriodicalId\":324891,\"journal\":{\"name\":\"2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS)\",\"volume\":\"52 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2012-09-05\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/MWSCAS.2012.6292067\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MWSCAS.2012.6292067","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Compact low-voltage CMOS analog divider using a four-quadrant multiplier and biasing control circuit
A compact low-voltage analog divider is presented. The design is based on a four-quadrant multiplier and a differential transconductance amplifier as basic building blocks operating in voltage mode. A biasing control circuit to set the dc operational point that requires very few devices and offers continuous-time operation is included. Experimental results of a test chip in 0.5μm CMOS technology verify the proposed operation.