Common mode implications of a dynamic latched comparator

A TGC-based dynamic comparator designed and simulated with HSPICE using 32/28 nm integrated CMOS PDK in SYNOPSYS environment in my recent work is further analyzed for common-mode implications to various factors like supply voltage, delay, power and dynamic range. The simulation results shows that the comparator topology is found to be well suited for the input common-mode range of 0.3 V to 0.8V and hence found to be sensitive to the differential input signal as weak as 0.5mV. The comparator is then also simulated over different supply voltage ranging from 1.2 V down to 0.3 V showing a huge power reduction with only a slight rise in delay from 60ps to 75ps approximately.