VLSI CMOS System/390处理器在卡级和系统级的测试

Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's Pub Date : 1991-04-15 DOI:10.1109/VTEST.1991.208169

W. Hartmann, C. Starke

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引用次数: 0

摘要

作者描述了作为IBM低端ES/9000系统一部分的S/390处理器的可测试性设计(DFT)和测试方法。该设计结合了内置的伪随机模式自检和边界扫描技术。自测允许将为组件级别生成的测试迁移到更高级别的封装(如印刷电路板和系统)。因此，测试高级封装的费用已大大减少，卡测试设备可以简化。此外，该应用策略提供了经济的诊断能力。

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Testing of VLSI CMOS System/390 processor at card and system level

The authors describe the design for testability (DFT) and testing methodology for the S/390 processor being part of IBM's low-end ES/9000 systems. The design incorporates built-in pseudo-random pattern self test and the boundary scan technique. Self test permits the migration of tests generated for the component level to higher-level packages such as printed circuit boards and the system. Consequently, the expense for testing of higher-level packages has been drastically reduced and the card test equipment can be simplified. In addition, the applied strategy offers economical diagnostic capability.<>

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来源期刊

Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's

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