早期可测试的可寻址逻辑(ETAL)测试结构:展示了在技术开发中使用替代逻辑生成学习测试结构

I. Ahsan, Daniel Greenslit, B. Evans, Toni Laaksonen, T. Gordon, Z. Song, Yandong Liu, J. Masnik, F. Barth, Shahrukh Khan, Joerg Winkler, Kannan Sekar, Neerja Bawaskar, Steve Crown, Kan Zhang, Martin O’tool, Teng-Yin Lin, M. Lagus, DK Sohn
{"title":"早期可测试的可寻址逻辑(ETAL)测试结构:展示了在技术开发中使用替代逻辑生成学习测试结构","authors":"I. Ahsan, Daniel Greenslit, B. Evans, Toni Laaksonen, T. Gordon, Z. Song, Yandong Liu, J. Masnik, F. Barth, Shahrukh Khan, Joerg Winkler, Kannan Sekar, Neerja Bawaskar, Steve Crown, Kan Zhang, Martin O’tool, Teng-Yin Lin, M. Lagus, DK Sohn","doi":"10.1109/ASMC.2019.8791769","DOIUrl":null,"url":null,"abstract":"Functional logic test structures with ATPG blocks and scan chains have been the traditional inline logic learning vehicle for technology learning and development. However, these test structures often need processing of wafers up to a higher BEOL processing level. They also need an elaborate diagnostic analysis to enable failure analysis. In this work, we showcase the use of an alternate logic test structure called the \"Early Testable Addressable Logic (ETAL)\" which is tested at an earlier test level and is easier to do failure analysis on. This structure can be used very effectively for yield learning at early stages of technology development as a complementary test structure to the traditional inline logic test structure.","PeriodicalId":287541,"journal":{"name":"2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Early Testable Addressable Logic (ETAL) Test Structure: Showcasing the use of an Alternate Logic Yield Learning Test Structure for Technology Development\",\"authors\":\"I. Ahsan, Daniel Greenslit, B. Evans, Toni Laaksonen, T. Gordon, Z. Song, Yandong Liu, J. Masnik, F. Barth, Shahrukh Khan, Joerg Winkler, Kannan Sekar, Neerja Bawaskar, Steve Crown, Kan Zhang, Martin O’tool, Teng-Yin Lin, M. Lagus, DK Sohn\",\"doi\":\"10.1109/ASMC.2019.8791769\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Functional logic test structures with ATPG blocks and scan chains have been the traditional inline logic learning vehicle for technology learning and development. However, these test structures often need processing of wafers up to a higher BEOL processing level. They also need an elaborate diagnostic analysis to enable failure analysis. In this work, we showcase the use of an alternate logic test structure called the \\\"Early Testable Addressable Logic (ETAL)\\\" which is tested at an earlier test level and is easier to do failure analysis on. This structure can be used very effectively for yield learning at early stages of technology development as a complementary test structure to the traditional inline logic test structure.\",\"PeriodicalId\":287541,\"journal\":{\"name\":\"2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2019-05-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASMC.2019.8791769\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASMC.2019.8791769","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0

摘要

具有ATPG模块和扫描链的功能逻辑测试结构一直是传统的内联逻辑学习工具,用于技术学习和开发。然而,这些测试结构通常需要将晶圆加工到更高的BEOL加工水平。他们还需要一个详细的诊断分析来支持故障分析。在这项工作中,我们展示了另一种逻辑测试结构的使用,称为“早期可测试的可寻址逻辑(ETAL)”,它在早期的测试级别上进行测试,并且更容易进行故障分析。这种结构可以非常有效地用于技术开发早期的良率学习,作为传统内联逻辑测试结构的补充测试结构。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Early Testable Addressable Logic (ETAL) Test Structure: Showcasing the use of an Alternate Logic Yield Learning Test Structure for Technology Development
Functional logic test structures with ATPG blocks and scan chains have been the traditional inline logic learning vehicle for technology learning and development. However, these test structures often need processing of wafers up to a higher BEOL processing level. They also need an elaborate diagnostic analysis to enable failure analysis. In this work, we showcase the use of an alternate logic test structure called the "Early Testable Addressable Logic (ETAL)" which is tested at an earlier test level and is easier to do failure analysis on. This structure can be used very effectively for yield learning at early stages of technology development as a complementary test structure to the traditional inline logic test structure.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术官方微信