SSC应用串行ATA信号生成和分析模拟测试仪资源

H. Okawara
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引用次数: 2

摘要

为了明确对电磁干扰(EMI)的规定,串行ATA (SATA)标准建议使用扩频时钟(SSC)来减少系统时钟频谱中的显著峰值。虽然高速串行接口的测试主要是通过数字测试仪来解决的,但是使用数字资源来生成和分析SSC应用的波形并不是一件容易的事情,而混合信号测试仪中的模拟资源可以很容易地处理这些信号。本工作的目的是建立使用任意波形发生器(AWG)生成SSC应用数据流的方法,并使用波形采样器分析SSC频率趋势。AWG生成750MHz时钟,与SSC对齐原语和伪随机二进制序列(PRBS)流。采样器分析时钟和对准原语,重建SSC频率趋势。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
SSC applied serial ATA signal generation and analysis by analog tester resources
In order to clear regulations on electro-magnetic interference (EMI), the serial ATA (SATA) standard recommends spread spectrum clocking (SSC) to reduce the significant peak in the spectrum of system clocks. Although testing of high-speed serial interface primarily addressed using digital testers, a SSC applied waveform is not an easy task for digital resources to generate and analyze, while analog resources in mixed signal testers can easily take care of such signals. The purpose of this work is to establish methodologies to generate a SSC applied data stream by using an arbitrary waveform generator (AWG) and to analyze the SSC frequency trend by using a waveform sampler. The AWG generates 750MHz clock, align primitives and pseudo random binary sequence (PRBS) stream with SSC. The sampler analyzes the clock and the align primitives reconstructing the SSC frequency trend.
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