Design of convolutional neural network SoC system based on FPGA

With the continuous development of neural network technology, it has been paid more and more attention in digital image processing. In this paper, the convolution neural network is designed on the programmable logic device (FPGA). Using the characteristics of the hardware circuit, the convolution kernel is implemented with the parallel data processing in the core and the parallel processing between the convolution cores. The double buffer is used to reduce the access to memory devices. At the same time, the characteristics of cyclic block and sparse matrix are used to optimize the network structure, improve the network speed and reduce the power consumption. ARM processor is used to preprocess the images and configure the corresponding registers to control the number of network layers of CNN network. The test results show that the recognition rate of handwritten numeral can reach 97% by using CNN accelerator based on FPGA. Meanwhile, the power consumption and speed are significantly improved, which meets the requirements of portable mobile devices.