正数加减法的高效硬件架构

Susheel Ujwal Siddamshetty, Srinivas Boppu, D. Ghosh
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引用次数: 0

摘要

本文针对最近发展起来的通用正数系统,提出了一种有效的加减法设计体系结构。位被设计为IEEE-754标准浮点数的直接插入式替代品。与浮点数相比,它们提供了令人信服的优势,例如更大的动态范围、比相同位宽的浮点数更高的精度、跨系统的按位计算相同的结果、没有溢出或下溢、逐渐减小的精度以及更简单的异常处理。单词大小$(N)$和指数大小$(ES)$定义了正数格式。它包括一个可变指数,由可变长度的体制位和指数位组成,最大大小可达$ES$ bits。这也导致尾数位的大小和位置的变化。这些运行时状态、指数和尾数字段长度的变化给设计算术硬件单元带来了挑战。虽然在文献中提出了一些加/减法,但它们不是100%准确的。然而,所提出的设计是有效的性能指标,如面积,延迟和泄漏功率。此外,与文献中提出的使用Cadence的45纳米标准电池库合成的最新设计相比,我们的设计具有100%的准确性,平均面积为15%,泄漏功率效率为23%,同时具有相似的关键路径延迟。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Efficient Hardware Architecture for Posit Addition/Subtraction
This paper proposes an efficient architecture for the design of adder/subtractor for the recently developed universal posit number system. Posits are designed as a direct drop-in replacement for IEEE-754 standard floating-point numbers. They provide compelling advantages over floats, such as larger dynamic range, higher accuracy than the same bit width floats, bit-wise identical results across systems, no overflow or underflow, tapered accuracy, and simpler exception handling. The word size $(N)$ and exponent size $(ES)$ define a posit format. It includes a variable exponent, consisting of variable length regime-bits and exponent-bits with a maximum size of up to $ES$ bits. This also leads to a change in the size and position of the mantissa bits. These run-time variations in the length of the regime, exponent, and mantissa fields pose a challenge while designing arithmetic hardware units. Though a few adder/subtractors are proposed in the literature, they are not 100% accurate. However, the proposed design is efficient in performance metrics such as area, delay, and leakage power. Furthermore, our design is 100% accurate, on an average 15 % area, and 23 % leakage power efficient while having a similar critical path delay when compared to the recent designs proposed in the literature when synthesized using Cadence's 45 nm standard cell library.
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