Efficient Hardware Architecture for Posit Addition/Subtraction

This paper proposes an efficient architecture for the design of adder/subtractor for the recently developed universal posit number system. Posits are designed as a direct drop-in replacement for IEEE-754 standard floating-point numbers. They provide compelling advantages over floats, such as larger dynamic range, higher accuracy than the same bit width floats, bit-wise identical results across systems, no overflow or underflow, tapered accuracy, and simpler exception handling. The word size $(N)$ and exponent size $(ES)$ define a posit format. It includes a variable exponent, consisting of variable length regime-bits and exponent-bits with a maximum size of up to $ES$ bits. This also leads to a change in the size and position of the mantissa bits. These run-time variations in the length of the regime, exponent, and mantissa fields pose a challenge while designing arithmetic hardware units. Though a few adder/subtractors are proposed in the literature, they are not 100% accurate. However, the proposed design is efficient in performance metrics such as area, delay, and leakage power. Furthermore, our design is 100% accurate, on an average 15 % area, and 23 % leakage power efficient while having a similar critical path delay when compared to the recent designs proposed in the literature when synthesized using Cadence's 45 nm standard cell library.